Log In to Connect With Members

View and follow other members, leave comments & more.

SEARCH ANYTHING

New Challenge !

Blogs

Semiconductor Blogs

Top 50 RTL Code open-source repositories

Why India’s Semiconductor Vision Matters: A Closer Look

Seagate sold its Soc unit to AVAGO, is Seagate no longer a semiconductor company??

WaferLab

Frequency to Period converter

Convert frequency to ns,ps,s

Period to frequency converter

Period to frequency calculator for physical design. Clock period to frequency

Chip Area Calculator

Width and length gives you area calculation with nm,mm scale unit

Chip Utilization Calculator

Calculate chip utilization

Reg2Reg Timing

Calculate setup and hold Timing for Flop to Flop path

Flop to Latch timing

Calculate Flop to Latch timing !

Half Cycle path Simulator

Calculate half cycle path setup and hold !

engineering calculator

A wide range of calculators for different purposes, including basic frequency to period, Die area calculator, Utilization calculations.

Wafer Lab

4XLearning Platform

4x Learning
Platform

vladimirovich_city_electronic_circuit_miniature_photographic_ci_a391a263-c7e5-4c23-8ba6-04

VLSI Forum

Forums act as repositories of knowledge for generations also help us on Problem-solving and troubleshooting. It will bring all the people together from different places.

What is the difference between final block and initial block

Radha A

Dash

Aug 15

How can we give delay value (based on which factory we will assign some value in this ) set_clock_gating_check value -steup [get_clocks clk]

Sanket Yawalkar

Dash

Jul 18

Why do we need endcap cells?

Semiconductor engineering

May 20

core boundary to die boundary

Radha A

Dash

Jul 16

How to fix clock gating setup violations, other than swaping and increasing the drive strength ofc cells ??

Radha A

Dash

Jul 16

What are the inputs for spef extraction ?

Brahmadev

Dash

Jul 13

[Physical-design] How do we decide operating frequency of the design ?

Ballu Sanjeev

Dash

Jun 10

Write a verilog code using function to generate numbers 1 2 2 3 3 3 4 4 4 4 5 5 5 5 5

Brahmadev

Dash

May 20

hold timing in ECF?

Jyun

Mar 19

RTL coding interview question and Answers pdf

Kesava Surendra Naidu

Jan 07

How You get the half cycle path between the two positive edge flops?

Darshan Goplani

Dec 13, 2023

i was asked this question in interview

Site Updates:

-> Added CRPR to setup and hold simulation.

-> Now members can create and post blogs.

-> Added features to calculate physical area and hard macro area

--> Added 4xLearning Platform

--> 200+ PD tricky Questions available.

--> Added tcl programming

Contact us: connect.vlsiyogi@gmail.com

HelpLine: +9108041225066

Policies,Terms and condition

About us

Building a strong Community of VLSI Engineers

VLSiYOGI

New Challenge !

Semiconductor Blogs

WaferLab

4x Learning
Platform

VLSI Forum

What is the difference between final block and initial block

How can we give delay value (based on which factory we will assign some value in this ) set_clock_gating_check value -steup [get_clocks clk]

Why do we need endcap cells?

core boundary to die boundary

How to fix clock gating setup violations, other than swaping and increasing the drive strength ofc cells ??

What are the inputs for spef extraction ?

[Physical-design] How do we decide operating frequency of the design ?

Write a verilog code using function to generate numbers 1 2 2 3 3 3 4 4 4 4 5 5 5 5 5

hold timing in ECF?

RTL coding interview question and Answers pdf

How You get the half cycle path between the two positive edge flops?

i was asked this question in interview

Contact us: connect.vlsiyogi@gmail.com

HelpLine: +9108041225066

LIVE GROUP MEMBERS

LOADING

JOIN OUR TELEGRAM CHANNEL VLSI FORUM https://t.me/vlsi_forum

Website visitor

New Challenge !

Semiconductor Blogs

WaferLab

4x Learning Platform

VLSI Forum

What is the difference between final block and initial block

How can we give delay value (based on which factory we will assign some value in this ) set_clock_gating_check value -steup [get_clocks clk]

Why do we need endcap cells?

core boundary to die boundary

How to fix clock gating setup violations, other than swaping and increasing the drive strength ofc cells ??

What are the inputs for spef extraction ?

[Physical-design] How do we decide operating frequency of the design ?

Write a verilog code using function to generate numbers 1 2 2 3 3 3 4 4 4 4 5 5 5 5 5

hold timing in ECF?

RTL coding interview question and Answers pdf

How You get the half cycle path between the two positive edge flops?

i was asked this question in interview

Contact us: connect.vlsiyogi@gmail.com HelpLine: +9108041225066

Website visitor

4x Learning
Platform

Contact us: connect.vlsiyogi@gmail.com

HelpLine: +9108041225066