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DFT
Design for Testability (DFT) in VLSI (Very Large Scale Integration) is a design technique that reduces the time.
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New Posts

Vamsi Krishna
Newbie
Dash
Aug 16
What is the difference between final block and initial block
RTL (Verilog ) Design
Multiole Final blocks execution happens in sequential manner Multiple initial blocks execution happens in parallel manner Both are correct Both are not correct
0
Radha A
Newbie
Dash
Aug 15
How can we give delay value (based on which factory we will assign some value in this ) set_clock_gating_check value -steup [get_clocks clk]
Physical Design Discussion
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Sanket Yawalkar
Newbie
Dash
Jul 18
Why do we need endcap cells?
Physical Design Discussion
As per my understanding, 1. They help to break n-well continuity which prevents and acts as a protective barrier from another tile. 2. The DRC of the endcap rule has been established to follow point 1. Fun facts: endcap is not needed on the bottom and top side of the block above 28nm Technologies.
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